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w w w w wm8734 stereo audio codec wolfson microelectronics ltd www.wolfsonmicro.com advanced information, november 2001, rev 2.2 copyright ? 2001 wolfson microelectronics ltd . description the wm8734 is a low power stereo codec ideal for md, cd-rw machines and dat recording applications. stereo line inputs are provided, along with a mute function and programmable line level volume control. stereo 24-bit multi-bit sigma delta adcs and dacs are used with oversampling digital interpolation and decimation filters. digital audio input word lengths from 16-32 bits and sampling rates from 8khz to 96khz are supported. stereo audio line level outputs are provided along with anti- thump mute and power up/down circuitry. the device is controlled via a 2 or 3 wire serial interface. the interface provides access to all features including level controls, mutes, de-emphasis and power management facilities. the device is available in 20-pin ssop or 5x5mm qfn packages. features ? audio performance ? 90db snr (?a? weighted @ 48khz) adc ? 100db snr (?a? weighted @ 48khz) dac ? 2.7 ? 3.6v digital supply operation ? 2.7 ? 3.6v analogue supply operation ? adc and dac sampling frequency: 8khz ? 96khz ? selectable adc high pass filter ? 2 or 3-wire mpu serial control interface ? programmable audio data interface modes ? i 2 s, left, right justified or dsp ? 16/20/24/32 bit word lengths ? master or slave clocking mode ? stereo audio inputs and outputs ? 20-pin ssop or 5x5mm qfn package options applications ? cd and minidisc recorder ? mp3 player / recorder block diagram adc adc digital filters digtal audio interface control interface dac dac csb sdin sclk rout lout rlinein llinein vmid dbvdd dgnd avdd agnd +12 to -34.5db, 1.5db steps +12 to -34.5db, 1.5db steps dcvdd adclrc daclrc bclk dacdat adcdat mclk mode mute mute vol w w w w wm8734 clkin divider (div x1, x2) vol
wm8734 advanced information w ai rev 2.2 november 2001 2 pin configuration ? ssop ordering information - ssop device temp. range package xWM8734EDS -10 to +70 o c 20-pin ssop 1 agnd 2 vmid 3 4 rlinein 5 6 7 8 mclk 9 llinein 10 mode csb sdin sclk dcvdd bclk dacdat dbvdd dgnd adcdat lout daclrc adclrc rout avdd 11 12 13 14 15 16 17 20 19 18 pin description - ssop pin name type description 1 dgnd ground digital gnd 2 dbvdd supply digital buffers vdd 3 bclk digital input/output digital audio bit clock, pull down, (see note 1) 4 dacdat digital input dac digital audio data input 5 daclrc digital input/output dac sample rate left/right clock. pull down (see note 1) 6 adcdat digital output adc digital audio data output 7 adclrc digital input/output adc sample rate left/right clock, pull down (see note 1) 8 lout analogue output left channel line output 9 rout analogue output right channel line output 10 avdd supply analogue vdd 11 agnd ground analogue gnd 12 vmid analogue output mid-rail reference decoupling point 13 rlinein analogue input right channel line input (ac coupled) 14 llinein analogue input left channel line input (ac coupled) 15 mode digital input control interface selection, pull up (see note 1) 16 csb digital input 3-wire mpu chip select / 2-wire mpu interface address selection, active low, pull up (see note 1) 17 sdin digital input/output 3-wire mpu data input / 2-wire mpu data input 18 sclk digital input 3-wire mpu clock input / 2-wire mpu clock input 19 mclk digital input master clock input (mclk) 20 dcvdd supply digital core vdd note: 1. pull up/down only present when control register interface active = 0 to conserve power.
wm8734 advanced information w ai rev 2.2 november 2001 3 pin configuration ? qfn ordering information - qfn device temp. range package xwm8734efl -10 to +70 o c 28-pin qfn (5x5x0.9mm) nc nc nc adclrc adcdat daclrc dacdat mclk nc dcvdd dgnd dbvdd nc bclk 28 27 26 25 24 23 22 nc rlinein llinein mode csb sdin sclk 1234567 8 10 9 11 14 13 12 21 20 19 18 17 16 15 nc vmid agnd avdd rout lout nc pin description - qfn pin name type description 1 mclk digital input master clock input (mclk) 2 nc do not connect test pin, must be left unconnected 3 dcvdd supply digital core vdd 4 dgnd ground digital gnd 5 dbvdd supply digital buffers vdd 6 nc do not connect test pin, must be left unconnected 7 bclk digital input/output digital audio bit clock, pull down, (see note 1) 8 dacdat digital input dac digital audio data input 9 daclrc digital input/output dac sample rate left/right clock. pull down (see note 1) 10 adcdat digital output adc digital audio data output 11 adclrc digital input/output adc sample rate left/right clock, pull down (see note 1) 12 nc do not connect test pin, must be left unconnected 13 nc do not connect test pin, must be left unconnected 14 nc do not connect test pin, must be left unconnected 15 nc do not connect test pin, must be left unconnected 16 lout analogue output left channel line output 17 rout analogue output right channel line output 18 avdd supply analogue vdd 19 agnd ground analogue gnd 20 vmid analogue output mid-rail reference decoupling point 21 nc do not connect test pin, must be left unconnected 22 nc do not connect test pin, must be left unconnected 23 rlinein analogue input right channel line input (ac coupled) 24 llinein analogue input left channel line input (ac coupled) 25 mode digital input control interface selection, pull up (see note 1) 26 csb digital input 3-wire mpu chip select / 2-wire mpu interface address selection, active low, pull up (see note 1) 27 sdin digital input/output 3-wire mpu data input / 2-wire mpu data input 28 sclk digital input 3-wire mpu clock input / 2-wire mpu clock input
wm8734 advanced information w ai rev 2.2 november 2001 4 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. condition min max digital supply voltage -0.3v +3.63v analogue supply voltage -0.3v +3.63v voltage range digital inputs dgnd -0.3v dvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v master clock frequency (see note 4) 40mhz operating temperature range, t a -10 c +70 c storage temperature prior to soldering 30 c max / 85% rh max storage temperature after soldering -65 c +150 c package body temperature (soldering 10 seconds) +240 c package body temperature (soldering 2 minutes) +183 c notes: 1. analogue and digital grounds must always be within 0.3v of each other. 2. the digital supply core voltage (dcvdd) must always be less than or equal to the analogue supply voltage (avdd) or digital supply buffer voltage (dbvdd). 3. the digital supply buffer voltage (dbvdd) must always be less than or equal to the analogue supply voltage (avdd). 4. when clkidiv2=1. recommended operating conditions parameter symbol test conditions min typ max unit digital supply range (core) dcvdd 2.7 3.3 3.6 v digital supply range (buffer) dbvdd 2.7 3.3 3.6 v analogue supply range avdd 2.7 3.3 3.6 v ground dgnd, agnd 0 v total analogue supply current iavdd dcvdd, dbvdd, avdd = 3.3v 16 ma digital supply current idcvdd, idbvdd dcvdd, dbvdd avdd = 3.3v 8 ma standby current consumption 5 ua
wm8734 advanced information w ai rev 2.2 november 2001 5 electrical characteristics test conditions avdd, dbvdd = 3.3v, agnd = 0v, dcvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit digital logic levels (cmos levels) input low level v il 0 .3 x dbvdd v input high level v ih 0 .7 x dbvdd v output low v ol 0.10 x dbvdd v output high v oh 0 .9 x dbvdd v power on reset threshold (dcvdd) dcvdd threshold on -> off v th 0.9 v hysteresis v ih 0.3 v dcvdd threshold off -> on v ol 0.6 v analogue reference levels reference voltage v vmid avdd/2 v potential divider resistance r vmid 50k ohms line input to adc input signal level (0db) v inline 1.0 avdd/3.3 vrms snr (note 1,3) a-weighted, 0db gain @ fs = 48khz 85 90 db snr (note 1,3) a-weighted, 0db gain @ fs = 96khz 90 db snr (note 1,3) a-weighted, 0db gain @ fs = 48khz, avdd = 2.7v 88 db dynamic range (note 3) dnr a-weighted, -60db full scale input 85 90 db thd -1db input, 0db gain -84 -74 db power supply rejection ratio pssr 1khz 100mvpp 50 db 20hz to 20khz 100mvpp 45 db adc channel separation 1khz input 90 db programmable gain maximum programmable gain minimum 1khz input rsource < 50 ohms +12 -34.5 db programmable gain step size guaranteed monotonic 1.5 db mute attenuation 0db, 1khz input 80 db 0db gain 20k 30k ohms input resistance r inline 12db gain 10k 15k ohms input capacitance c inline 10 pf
wm8734 advanced information w ai rev 2.2 november 2001 6 test conditions avdd, dbvdd = 3.3v, agnd = 0v, dcvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit line output for dac playback only (load = 47k ohms. 50pf) 0dbfs full scale output voltage at line outputs 1.0 x avdd/3.3 vrms snr (note 1,2,3) a-weighted, @ fs = 48khz 90 100 db snr (note 1,2,3) a-weighted @ fs = 96khz 98 db snr (note 1,2,3) a-weighted, @ fs = 48khz, avdd = 2.7v 93 db dynamic range (note 3) dnr a-weighted, -60db full scale input 85 95 db 1khz, 0dbfs -88 -80 db thd 1khz, -3dbfs -92 db 1khz 100mvpp 50 db power supply rejection ratio pssr 20hz to 20khz 100mvpp 45 db dac channel separation 100 db notes: 1. ratio of output level with 1khz full scale input, to the output level with the input short circuited, measured ?a? weighted over a 20hz to 20khz bandwidth using an audio analyser. 2. ratio of output level with 1khz full scale input, to the output level with all zeros into the digital input, measured ?a? weighted over a 20hz to 20khz bandwidth. 3. all performance measurements done with 20khz low pass filter, and where noted an a-weight filter. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 4. vmid decoupled with 10uf and 0.1uf capacitors (smaller values may result in reduced performance). terminology 1. signal-to-noise ratio (db) - snr is a measure of the difference in level between the full scale output and the output with no signal applied. (no auto-zero or automute function is employed in achieving these results). 2. dynamic range (db) - dnr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd+n @ -60db= -32db, dr= 92db). 3. thd+n (db) - thd+n is a ratio, of the rms values, of (noise + distortion)/signal. 4. stop band attentuation (db) ? is the degree to which the frequency spectrum is attenuated (outside audio band). 5. channel separation (db) - also known as cross-talk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full scale signal down one channel and measuring the other. 6. pass-band ripple ? any variation of the frequency response in the pass-band region.
wm8734 advanced information w ai rev 2.2 november 2001 7 master clock timing mclk t mclkl t mclkh t mclky figure 1 system clock timing requirements test conditions avdd, dbvdd = 3.3v, agnd = 0v, dcvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit system clock timing information mclk system clock pulse width high t xtih 18 ns mclk system clock pulse width low t xtil 18 ns mclk system clock cycle time t xtiy 54 ns mclk duty cycle 40:60 60:40 digital audio interface ? master mode bclk adcdat adclrc dacdat daclrc wm8734 codec dsp encoder/ decoder figure 2 master mode connection
wm8734 advanced information w ai rev 2.2 november 2001 8 bclk (output) adcdat adclrc/ daclrc (outputs) t dl dacdat t dda t dht t dst figure 3 digital audio data timing ? master mode test conditions avdd, dbvdd = 3.3v, agnd = 0v, dcvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information adclrc/daclrc propagation delay from bclk falling edge t dl 0 10 ns adcdat propagation delay from bclk falling edge t dda 0 10 ns dacdat setup time to bclck rising edge t dst 10 ns dacdat hold time from bclk rising edge t dht 10 ns digital audio interface ? slave mode bclk adcdat adclrc dacdat daclrc wm8734 codec dsp encoder/ decoder figure 4 slave mode connection
wm8734 advanced information w ai rev 2.2 november 2001 9 bclk daclrc/ adclrc t bch t bcl t bcy dacdat adcdat t lrsu t ds t lrh t dh t dd figure 5 digital audio data timing ? slave mode test conditions avdd, dbvdd = 3.3v, agnd = 0v, dcvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns daclrc/adclrc set-up time to bclk rising edge t lrsu 10 ns daclrc/adclrc hold time from bclk rising edge t lrh 10 ns dacdat set-up time to bclk rising edge t ds 10 ns dacdat hold time from bclk rising edge t dh 10 ns adcdat propagation delay from bclk falling edge t dd 0 10 ns
wm8734 advanced information w ai rev 2.2 november 2001 10 mpu interface timing csb sclk sdin t csl t dho t dsu t csh t scy t sch t scl t scs lsb t css figure 6 program register input timing ? 3-wire mpu serial control mode test conditions avdd, dbvdd = 3.3v, agnd = 0v, dcvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit program register input information sclk rising edge to csb rising edge t scs 60 ns sclk pulse cycle time t scy 80 ns sclk pulse width low t scl 20 ns sclk pulse width high t sch 20 ns sdin to sclk set-up time t dsu 20 ns sclk to sdin hold time t dho 20 ns csb pulse width low t csl 20 ns csb pulse width high t csh 20 ns csb rising to sclk rising t css 20 ns
wm8734 advanced information w ai rev 2.2 november 2001 11 sdin sclk t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 10 figure 7 program register input timing ? 2-wire mpu serial control mode test conditions avdd, dbvdd = 3.3v, agnd = 0v, dcvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit program register input information sclk frequency 0 400 khz sclk low pulsewidth t 1 600 ns sclk high pulsewidth t 2 1.3 us hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 10 900 ns
wm8734 advanced information w ai rev 2.2 november 2001 12 device description the wm8734 is a high performance audio codec designed specifically for audio applications that require recording and playback features. the codec includes line inputs to the on-board adc, line outputs from the on-board dac, a configurable digital audio interface and a choice of 2 or 3 wire mpu control interface. it is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and dsps. the codec includes a stereo low noise input. line inputs have +12db to -34db logarithmic volume level adjustments and mute. all the required input filtering is contained within the device. the on-board stereo analogue to digital converter (adc) is of a high quality using a multi-bit high- order oversampling architecture delivering optimum performance with low power consumption. the output from the adc is available on the digital audio interface. the adc includes an optional digital high pass filter to remove unwanted dc components from the audio signal. the on-board digital to analogue converter (dac) accepts digital audio from the digital audio interface. digital filter de-emphasis at 32khz, 44.1khz and 48khz can be applied to the digital data under software control. the dac employs a high quality multi-bit high-order oversampling architecture to again deliver optimum performance with low power consumption. special techniques allow the audio to be muted and the device safely placed into standby, sections of the device powered off and volume levels adjusted without any audible cli cks, pops or zipper noises. therefore standby and power off modes may be used dynamically under software control, whenever recording or playback is not required. the device caters for a number of different sampling rates including industry standard 8khz, 32khz, 44.1khz, 48khz, 88.2khz and 96khz. the digital filters used for both record and playback are optimised for each sampling rate used. the digitised output is available in a number of audio data formats i 2 s, dsp mode (a burst mode in which frame sync plus 2 data packed words are transmitted), msb-first, left justified and msb-first, right justified. the digital audio interface can operate in both master or slave modes. the software control uses either a 2 or 3-wire mpu interface. audio signal path line inputs the wm8734 provides left and right channel line inputs (rlinein and llinein). the inputs are high impedance and low capacitance, thus ideally suited to receiving line level signals from external hi-fi or audio equipment. both line inputs include independent programmable volume level adjustments and input mute. the scheme is illustrated in figure 8. passive rf and active anti-alias filters are also incorporated within the line inputs. these prevent high frequencies aliasing into the audio band or otherwise degrading performance.
wm8734 advanced information w ai rev 2.2 november 2001 13 12.5k vmid linein to adc figure 8 line input schematic the gain between the line inputs and the adc is logarithmically adjustable from +12db to ?34.5db in 1.5db steps under software control. the adc full scale input is 1.0v rms at avdd = 3.3 volts. any voltage greater than full scale will possibly overload the adc and cause distortion. note that the full scale input tra cks directly with avdd. the gain is i ndependently adjustable on both right and left line inputs. however, by setting the inboth bit whilst programming the volume control, both channels are simultaneously updated with the same value. use of inboth reduces the required number of software writes required. the line inputs to the adc can be muted in the analogue domain under software control. the software control registers are shown below. register address bit label default description 4:0 linvol[4:0] 10111 ( 0db ) left channel line input volume control 11111 = +12db . . 1.5db steps down to 00000 = -34.5db 7 linmute 1 left channel line input mute to adc 1 = enable mute 0 = disable mute 0000000 left line in 8 lrinboth 0 left to right channel line input volume and mute data load control 1 = enable simultaneous load of linvol[4:0] and linmute to rinvol[4:0] and rinmute 0 = disable simultaneous load 4:0 rinvol[4:0] 10111 ( 0db ) right channel line input volume control 11111 = +12db . .1.5db steps down to 00000 = -34.5db 7 rinmute 1 right channel line input mute to adc 1 = enable mute 0 = disable mute 0000001 right line in 8 rlinboth 0 right to left channel line input volume and mute data load control 1 = enable simultaneous load of rinvol[4:0] and rinmute to linvol[4:0] and linmute 0 = disable simultaneous load table 1 line input software control
wm8734 advanced information w ai rev 2.2 november 2001 14 the line inputs are biased internally through the operational amplifier to vmid. whenever the line inputs are muted or the device placed into standby mode, the line inputs are kept biased to vmid using special anti-thump circuitry. this reduces any audible cli cks that may otherwise be heard when re-activating the inputs. the external components required to complete the line input application is shown in the figure 9. agnd agnd r1 r2 c1 c2 agnd linein figure 9 line input application drawing for interfacing to a typical cd system, it is recommended that the input is scaled to ensure that there is no clipping of the signal. r1 = 5k, r2 = 5k, c1 = 47pf, c2 = 470nf (10v npo ceramic type). r1 and r2 form a resistive divider to attenuate the 2 vrms output from a cd player to a 1 vrms level, so avoiding overloading the inputs. r2 also provides a discharge path for c2, thus preventing the input to c2 charging to an excessive voltage which may otherwise damage any equipment connected that is not suitably protected against high voltages. c1 forms an rf low pass filter for increasing the rejection of rf interference picked up on any cables. c2 forms a dc blocking capacitor to remove the dc path between the wm8734 and the driving audio equipment. c2 together with the input impedance of the wm8734 form a high pass filter. adc the wm8734 uses a multi-bit oversampled sigma-delta adc. a single channel of the adc is illustrated in the figure 10. from line input analog integrator multi bits to adc digital filters figure 10 multi-bit oversampling sigma delta adc schematic
wm8734 advanced information w ai rev 2.2 november 2001 15 the use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. the adc full scale input is 1.0v rms at avdd = 3.3 volts. any voltage greater than full scale will possibly overload the adc and cause distortion. note that the full scale input tra cks directly with avdd. the device employs a pair of adcs. the two channels cannot be selected independently. the digital data from the adc is fed for signal processing to the adc filters. adc filters the adc filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the adc to the correct sampling frequency to be output on the digital audio interface. figure 11 illustrates the digital filter path. from adc digital hpf digital decimation filter to digital audio interface digital decimator hpfen figure 11 adc digital filter the adc digital filters contain a digital high pass filter, selectable via software control. the high-pass filter response detailed in digital filter characteristics. when the high-pass filter is enabled the dc offset is continuously calculated and subtracted from the input signal. by setting hpor the last calculated dc offset value is stored when the high-pass filter is disabled and will continue to be subtracted from the input signal. if the dc offset changed, the stored and subtracted value will not change unless the high-pass filter is enabled. the software control is shown in table 2. register address bit label default description 0 adchpd 0 adc high pass filter enable (digital) 1 = disable high pass filter 0 = enable high pass filter 00000101 digital audio path control 4 hpor 0 store dc offset when high pass filter disabled 1 = store offset 0 = clear offset table 2 adc software control there are several types of adc filters, frequency and phase responses of these are shown in digital filter characteristics. the filter types are automatically configured depending on the sample rate chosen. refer to the sample rate section for more details. dac filters the dac filters perform true 24 bit signal processing to convert the incoming digital audio data from the digital audio interface at the specified sample rate to multi-bit oversampled data for processing by the analogue dac. figure 12 illustrates the dac digital filter path.
wm8734 advanced information w ai rev 2.2 november 2001 16 from digital audio interface mute digital interpolation filter to line outputs digital de_emphasis deemp dacmu figure 12 dac filter schematic the dac digital filter can apply digital de-emphasis under software control, as shown in table 3. the dac can also perform a soft mute where the audio data is digitally brought to a mute level. this removes any abrupt step changes in the audio that might otherwise result in audible cli cks in the audio outputs. register address bit label default description 2:1 deemp[1:0] 00 de-emphasis control (digital) 11 = 48khz 10 = 44.1khz 01 = 32khz 00 = disable 0000101 digital audio path control 3 dacmu 1 dac soft mute control (digital) 1 = enable soft mute 0 = disable soft mute table 3 dac software control dac the wm8734 employs a multi-bit sigma delta oversampling digital to analogue converter. the scheme for the converter is illustrated in figure 13. from dac digital filters to line output figure 13 multi-bit oversampling sigma delta schematic the dac converts the multi-level digital audio data stream from the dac digital filters into high quality analogue audio.
wm8734 advanced information w ai rev 2.2 november 2001 17 line outputs the wm8734 provides two low impedance line outputs llineout and rlineout, suitable for driving typical line loads of impedance 10k and capacitance 50pf. the line output is used to selectively sum the outputs from the dac or/and the line inputs in bypass mode. the llineout and rlineout outputs are only available at a line output level and are not level adjustable in the analogue domain, having a fixed gain of 0db. the level is fixed such that at the dac full scale level the output level is vrms at avdd = 3.3 volts. note that the dac full scale level tracks directly with avdd. the scheme is shown in figure 14. the line output includes a low order audio low pass filter for removing out-of band components from the sigma-delta dac. therefore no further external filtering is required in most applications. vmid lineout from dac to headphone amp dacsel figure 14 line output schematic the line output is muted by either muting the dac (analogue) or soft muting (digital). refer to the dac section for more details. whenever the dac is muted or the device placed into standby mode the dc voltage is maintained at the line outputs to prevent any audible cli cks from being present. the software control for the line outputs is shown in table 4. register address bit label default description 0000100 analogue audio path control 4 dacsel 0 dac select 1 = select dac 0 = don?t select dac table 4 output software control the recommended external components are shown in figure 15. agnd r1 c1 agnd lineout r2
wm8734 advanced information w ai rev 2.2 november 2001 18 figure 15 line outputs application drawing recommended values are c1 = 470nf (10v npo type), r1 = 47kohms, r2 = 100 ohms c1 forms a dc blocking capacitor to the line outputs. r1 prevents the output voltage from drifting so protecting equipment connected to the line output. r2 forms a de-coupling resistor preventing abnormal loads from disturbing the device. note that poor choice of dielectric material for c1 can have dramatic effects on the measured signal distortion at the output. device operation device resetting the wm8734 contains a power on reset circuit that resets the internal state of the device to a known condition. the power on reset is applied as dcvdd powers on and released only after the voltage level of dcvdd crosses a minimum turn off threshold. if dcvdd later falls below a minimum turn on threshold voltage then the power on reset is re-applied. the threshold voltages and associated hysteresis are shown in the electrical characteristics table. the user also has the ability to reset the device to a known state under software control as shown in the table below. register address bit label default description 0001111 reset register 8:0 reset not reset reset register writing 00000000 to register resets device table 5 software control of reset when using the software reset. in 3-wire mode the reset is applied on the rising edge of csb and released on the next rising edge of sclk. in 2-wire mode the reset is applied for the duration of the ack signal (approximately 1 sclk period, refer to figure 23). clocking schemes in a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. this clock is often referred to as the audio system?s master clock. to allow wm8734 to be used in a centrally clocked system, the wm8734 is capable of deriving the sample rate clock from this master clock (master mode) or receiving the sample rate clock from an external source (slave mode). core clock the wm8734 dsp core can be clocked either by mclk or mclk divided by 2. this is controlled by software as shown in table 6 below. register address bit label default description 0001000 sampling control 6 clkidiv2 0 core clock divider select 1 = core clock is mclk divided by 2 0 = core clock is mclk table 6 software control of core clock having a programmable mclk divider allows the device to be used in applications where higher frequency master clo cks are available. for example the device can s upport 512fs master clo cks whilst fundamentally operating in a 256fs mode. digital audio interfaces wm8734 may be operated in either one of the 4 offered audio interface modes. these are: ? right justified ? left justified ? i 2 s ? dsp mode all four of these modes are msb first and operate with data 16 to 32 bits, except right justified mode which does not support 32 bits.
wm8734 advanced information w ai rev 2.2 november 2001 19 the digital audio interface takes the data from the internal adc digital filter and places it on the adcdat output. adcdat is the formatted digital audio data stream output from the adc digital filters with left and right channels multiplexed together. adclrc is an alignment clock that controls whether left or right channel data is present on the adcdat lines. adcdat and adclrc are synchronous with the bclk signal with each data bit transition signified by a bclk high to low transition. bclk maybe an input or an output dependent on whether the device is in master or slave mode. refer to the master/slave operation section. the digital audio interface also receives the digital audio data for the internal dac digital filters on the dacdat input. dacdat is the formatted digital audio data stream output to the dac digital filters with left and right channels multiplexed together. daclrc is an alignment clock that controls whether left or right channel data is present on datdat. dacdat and daclrc are synchronous with the bclk signal with each data bit transition signified by a bclk transition. dacdat is always an input. bclk and daclrc are either outputs or inputs depending whether the device is in master or slave mode. refer to the master/slave operation section there are four digital audio interface formats accommodated by the wm8734. these are shown in the figures below. refer to the electrical characteristic section for timing information. left justified mode is where the msb is available on the first rising edge of bclk following a adclr or daclrc transition. left channel right channel daclrc/ adclrc bclk dacdat/ adcdat 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb figure 16 left justified mode i 2 s mode is where the msb is available on the 2 nd rising edge of bclk following a lrclk transition. left channel right channel daclrc/ adclrc bclk dacdat/ adcdat 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb 1 bclk 1 bclk figure 17 i 2 s mode right justified mode is where the lsb is available on the rising edge of bclk preceding a lrclk transition, yet msb is still transmitted first.
wm8734 advanced information w ai rev 2.2 november 2001 20 left channel right channel daclrc/ adclrc bclk dacdat/ adcdat 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb figure 18 right justified mode dsp mode is where the left channel msb is available on either the 1 st or 2 nd rising edge of bclk (selectable by lrp) following a lrc transition high. right channel data immediately follows left channel data. left channel right channel daclrc/ adclrc bclk dacdat/ adcdat n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 1 bclk input word length (iwl) note: input word length is defined by the iwl register, lrp = 1 1/fs figure 19 dsp mode in all modes daclrc and adclrc must always change on the falling edge of bclk, refer to figure 16, figure 17, figure 18 and figure 19. operating the digital audio interface in dsp mode allows ease of use for supporting the various sample rates and word lengths. the only requirement is that all data is transferred within the correct number of bclk cycles to suit the chosen word length. in order for the digital audio interface to offer similar support in the three other modes (left justified, i 2 s and right justified), the daclrc, adclrc and bclk frequencies, continuity and mark-space ratios need more careful consideration. in slave mode, daclrc and adclrc inputs are not required to have a 50:50 mark-space ratio. bclk input need not be continuous. it is however required that there are sufficient bclk cycles for each daclrc/adclrc transition to clock the chosen data word length.
wm8734 advanced information w ai rev 2.2 november 2001 21 in master mode, daclrc and adclrc will be output with a 50:50 mark-space ratio with bclk output at 64fs. the adc and dac digital audio interface modes are software configurable as indicated in table 7. note that dynamically changing the software format may result in erroneous operation of the interfaces and is therefore not recommended. the length of the digital audio data is programmable at 16/20/24 or 32 bits. refer to the software control table below. the data is signed 2?s complement. both adc and dac are fixed at the same data length. the adc and dac digital filters process data using 24 bits. if the adc is programmed to output 16 or 20 bit data then it strips the lsbs from the 24 bit data. if the adc is programmed to output 32 bits then it pa cks the lsbs with zeros. if the dac is programmed to receive 16 or 20 bit data, the wm8734 pa cks the lsbs with zeros. if the dac is programmed to receive 32 bit data, then it strips the lsbs. the dac outputs can be swapped under software control using lrp and lrswap as shown in table 7. stereo samples are normally generated as a left/right sampled pair. lrswap reverses the order of that a left sample goes to the right dac output and a right sample goes to the left dac output. lrp swaps the phasing so that a right/left sampled pair is expected and preserves the correct channel phase difference. to accommodate system timing requirements the interpretation of bclk may be inverted, this is controlled vias the software shown in table 6. this is especially appropriate for dsp mode. adcdat lines are always outputs. they power up and return from standby low. dacdat is always an input. it is expected to be set low by the audio interface controller when the wm8734 is powered off or in standby. adclrc, daclrc and bclk can be either outputs or inputs depending on whether the device is configured as a master or slave. if the device is a master then the adclrc, daclrc and bclk signals are outputs that default low. if the device is a slave then the adclrc, daclrc and bclk are inputs.
wm8734 advanced information w ai rev 2.2 november 2001 22 register address bit label default description 1:0 format[1:0] 10 audio data format select 11 = dsp mode, frame sync + 2 data packed words 10 = i 2 s format, msb-first left-1 justified 01 = msb-first, left justified 00 = msb-first, right justified 3:2 iwl[1:0] 10 input audio data bit length select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits 4 lrp 0 daclrc phase control (in left, right or i 2 s modes) 1 = right channel dac data when daclrc high 0 = right channel dac data when daclrc low (opposite phasing in i 2 s mode) or dsp mode a/b select (in dsp mode only) 1 = msb is available on 2nd bclk rising edge after adclrc/daclrc rising edge 0 = msb is available on 1st bclk rising edge after adclrc/daclrc rising edge 5 lrswap 0 dac left right clock swap 1 = right channel dac data left 0 = right channel dac data right 6 ms 0 master slave mode control 1 = enable master mode 0 = enable slave mode 0000111 digital audio interface format 7 bclkinv 0 bit clock invert 1 = invert bclk 0 = don?t invert bclk table 7 digital audio interface control note: if right justified 32 bit mode is selected then the wm8734 defaults to 24 bits. master and slave mode operation the wm8734 can be configured as either a master or slave mode device. as a master mode device the wm8734 controls sequencing of the data and clo cks on the digital audio interface. as a slave device the wm8734 responds with data to the clo cks it receives over the digital audio interface. the mode is set with the ms bit of the control register as shown in table 8. register address bit label default description 0000111 digital audio interface format 6 ms 0 master slave mode control 1 = enable master mode 0 = enable slave mode table 8 programming master/slave modes
wm8734 advanced information w ai rev 2.2 november 2001 23 as a master mode device the wm8734 controls the sequencing of data transfer (adcdat, dacdat) and output of clo cks (bclk, adclrc, daclrc) over the digital audio interface. it uses the timing generated from either its on-board crystal or the mclk input as the reference for the clock and data transitions. this is illustrated in figure 20. adcdat is always an output from and dacdat is always an input to the wm8734 independent of master or slave mode. bclk adcdat adclrc dacdat daclrc wm8734 codec dsp encoder/ decoder figure 20 master mode as a slave device the wm8734 sequences the data transfer (adcdat, dacdat) over the digital audio interface in response to the external applied clo cks (bclk, adclrc, daclrc). this is illustrated in figure 21. bclk adcdat adclrc dacdat daclrc wm8734 codec dsp encoder/ decoder figure 21 slave mode note that the wm8734 relies on controlled phase relationships between audio interface bclk, daclrc and the master mclk. to avoid any timing hazards, refer to the timing section for detailed information. audio data sampling rates the wm8734 provides for two modes of operation (normal and usb) to generate the required dac and adc sampling rates. normal and usb modes are programmed under software control according to the table below. in normal mode, the user controls the sample rate by using an appropriate mclk or crystal frequency and the sample rate control register setting. the wm8734 can support sample rates from 8ks/s up to 96ks/s. in usb mode, the user must use a fixed mlck or crystal frequency of 12mhz to generate sample rates from 8ks/s to 96ks/s. it is called usb mode since the common usb (universal serial bus) clock is at 12mhz and the wm8734 can be directly used within such systems. wm8734 can generate all the normal audio sample rates from this one master clock frequency, removing the need for different master clocks or pll circuits.
wm8734 advanced information w ai rev 2.2 november 2001 24 uniquely, the wm8734 offers the user the ability to sample the adc and dac at different rates under software control in both normal and usb modes. the reduces the burden on any controlling dsp. however, the signal processing in the adc and dac over-sampling filters is tightly coupled together in order to minimise power consumption. to this end, only the combinations of sample rates listed in the following sections are supported. note that these rates supported are anticipated to be the likely combinations used in typical audio systems. register address bit label default description 0 usb/ normal 0 mode select 1 = usb mode (250/272fs) 0 = normal mode (256/384fs) 1 bosr 0 base over-sampling rate usb mode 0 = 250fs 1 = 272fs normal mode 0 = 256fs 1 = 384fs 0001000 sampling control 5:2 sr[3:0] 0000 adc and dac sample rate control; see usb mode and normal mode sample rate sections for operation table 9 sample rate control sample rate setting in normal mode mclk/crystal oscillator is set up according to the desired sample rates of the adc and dac. for adc or dac sampling rates of 8, 32, 48 or 96khz, mclk frequencies of either 12.288mhz (256fs) or 18.432mhz (384fs) can be used. for adc or dac sampling rates of 8, 44.1 or 88.2khz from mclk frequencies of either 11.2896mhz (256fs) or 16.9344mhz (384fs) can be used. the table below should be used to set up the device to work with the various sample rate combinations. for example if the user wishes to use the wm8734 in normal mode with the adc and dac sample rates at 48khz and 48khz respectively then the device should be programmed with bosr = 0, sr3 = 0, sr2 = 0, sr1 = 0 and sr0 = 0 with a 12.288mhz mclk or with bosr = 1, sr3 = 0, sr2 = 0, sr1 = 0 and sr0 = 0 with a 18.432mhz mclk. the adc and dac will then operate with a digital filter of type 1, refer to digital filter characteristics section for an explanation of the different filter types.
wm8734 advanced information w ai rev 2.2 november 2001 25 sampling rate adc dac mclk frequency sample rate register settings digital filter type khz khz mhz bosr sr3 sr2 sr1 sr0 12.288 0 0 0 0 0 48 48 18.432 1 0 0 0 0 1 12.288 0 0 0 0 1 48 8 18.432 1 0 0 0 1 1 12.288 0 0 0 1 0 8 48 18.432 1 0 0 1 0 1 12.288 0 0 0 1 1 8 8 18.432 1 0 0 1 1 1 12.288 0 0 1 1 0 32 32 18.432 1 0 1 1 0 1 12.288 0 0 1 1 1 96 96 18.432 1 0 1 1 1 2 11.2896 0 1 0 0 0 44.1 44.1 16.9344 1 1 0 0 0 1 11.2896 0 1 0 0 1 44.1 8 (note 1) 16.9344 1 1 0 0 1 1 11.2896 0 1 0 1 0 8 (note 1) 44.1 16.9344 1 1 0 1 0 1 11.2896 0 1 0 1 1 8 (note 1) 8 (note 1) 16.9344 1 1 0 1 1 1 11.2896 0 1 1 1 1 88.2 88.2 16.9344 1 1 1 1 1 2 table 10 normal mode sample rate look-up table notes: 1. 8k not exact, actual = 8.018khz 2. all other combinations of bosr and sr[3:0] that are not in the truth table are invalid the bosr bit represents the base over-sampling rate. this is the rate that the wm8734 digital signal processing is carried out at. in normal mode, with bosr = 0, the base over-sampling rate is at 256fs, with bosr = 1, the base over-sampling rate is at 384fs. this can be used to determine the actual audio data rate produced by the adc and required by the dac. example scenarios are: 1. with a requirement that the adc data rate is 8khz and dac data rate is 48khz, then choosing mclk = 12.288mhz the device is programmed with bosr = 0 (256fs), sr3 = 0, sr2 = 0, sr1 = 1, sr0 = 0.the adc output data rate will then be exactly 8khz (derived from 12.288mhz/256 x1/6) and the dac expects data at exactly 48khz (derived from 12.288mhz/256) 2. with a requirement that adc data rate is 8khz and dac data rate is 44.1khz, then choosing mclk = 16.9344mhz the device is programmed with bosr = 1 (384fs), sr3 = 1, sr2 = 0, sr1 = 0, sr0 = 1. the adc will no longer output data at exactly 8.000khz, instead it will be 8.018khz (derived from 16.9344mhz/384 x 2/11), the dac still is at exactly 44.1khz (derived from 16.9344mhz/384). a slight (sub 0.5%) pitch shift will therefore result in the 8khz audio data and (importantly) the user must ensure that the data across the digital interface is correctly synchronised at the 8.018khz rate.
wm8734 advanced information w ai rev 2.2 november 2001 26 the exact sample rates achieved are defined by the relationships in table 11 below. actual sampling rate bosr=0 (256fs) bosr=1 (384fs) target sampling rate mclk=12.288 mclk=11.2896 mclk=18.432 mclk=16.9344 khz khz khz khz khz 8 8.018 8 8.018 8 12.288mhz/256 x 1/6 11.2896mhz/256 x 2/11 18.432mhz/384 x 1/6 16.9344mhz/384 x 2/11 32 32 32 12.288mhz/256 x 2/3 not available 18.432mhz/384x 2/3 not available 44.1 44.1 44.1 not available 11.2896mhz/256 not available 16.9344mhz /384 48 48 48 12.288mhz/256 not available 18.432mhz/384 not available 88.2 88.2 88.2 not available 11.2896mhz/384 x 2 not available 16.9344mhz /384 x 2 96 96 96 12.288mhz/256 x 2 not available 18.432mhz/384 x 2 not available table 11 normal mode actual sample rates 128/192fs normal mode the normal mode sample rates are designed for standard 256fs and 384fs mclk rates. however the wm8734 is also capable of being clocked from a 128 or 192fs mclk for application over limited sampling rates as shown in the table below. sampling rate adc dac mclk frequency sample rate register settings digital filter type khz khz mhz bosr sr3 sr2 sr1 sr0 6.144 0 0 1 1 1 48 48 9.216 1 0 1 1 1 2 5.6448 0 1 1 1 1 44.1 44.1 8.4672 1 1 1 1 1 2 table 12 128fs normal mode sample rate look-up table 512/768fs normal mode 512 fs and 768 fs mclk rates can be accommodated by using the clkidiv2 bit. the core clock to the dsp will be divided by 2 so an external 512/768 mclk will become 256/384 fs internally and the device otherwise operates as in table 8 but with mclk at twice the specified rate. see table 6 for software control.
wm8734 advanced information w ai rev 2.2 november 2001 27 usb mode sample rates in usb mode the mclk/crystal oscillator input is 12mhz only. sampling rate adc dac mclk frequency sample rate register settings digital filter type khz khz mhz bosr sr3 sr2 sr1 sr0 48 48 12.000 0 0 0 0 0 0 44.1 (note 2) 44.1 (note 2) 12.000 1 1 0 0 0 1 48 8 12.000 0 0 0 0 1 0 44.1 (note 2) 8 ( n ote 1 ) 12.000 1 1 0 0 1 1 8 48 12.000 0 0 0 1 0 0 8 ( n ote 1 ) 44.1 (note 2) 12.000 1 1 0 1 0 1 8 8 12.000 0 0 0 1 1 0 8 ( n ote 1 ) 8 ( n ote 1 ) 12.000 1 1 0 1 1 1 32 32 12.000 0 0 1 1 0 0 96 96 12.000 0 0 1 1 1 3 88.2 (note 3) 88.2 (note 3) 12.000 1 1 1 1 1 2 table 13 usb mode sample rate look-ip table notes: 1. 8k not exact, actual = 8.021khz 2. 44.1k not exact, actual = 44.118khz 3. 88.1k not exact, actual = 88.235khz 4. all other combinations of bosr and sr[3:0] that are not in the truth table are invalid the table above can be used to set up the device to work with various sample rate combinations. for example if the user wishes to use the wm8734 in usb mode with the adc and dac sample rates at 48khz and 48khz respectively then the device should be programmed with bosr = 0, sr3 = 0, sr2 = 0, sr1 = 0 and sr0 = 0. the adc and dac will then operate with a digital filter of type 0, refer to digital filter characteristics section for an explanation of the different filter types. the bosr bit represents the base over-sampling rate. this is the rate that the wm8734 digital signal processing is carried out at and the sampling rate will always be a sub-multiple of this. in usb mode, with bosr = 0, the base over-sampling rate is defined at 250fs, with bosr = 1, the base over- sampling rate is defined at 272fs. this can be used to determine the actual audio sampling rate produced by the adc and required by the dac. example scenarios are, :- 1. with a requirement that the adc data sampling rate is 8khz and dac data sampling rate is 48khz the device is programmed with bosr = 0 (250fs), sr3 = 0, sr2 = 0, sr1 = 1, sr0 = 0.the adc will then be exactly 8khz ( derived from 12mhz/250 x 1/6 ) and the dac expects data at exactly 48khz ( derived from 12mhz/250 ). 2. with a requirement that adc data rate is 8khz and dac data rate is 44.1khz the device is programmed with bosr = 0 (272fs), sr3 = 0, sr2 = 0, sr1 = 1, sr0 = 0. the adc will not output data at exactly 8khz, instead it will be 8.021khz ( derived from 12mhz/272 x 2/11 ) and the dac at 44.118khz ( derived from 12mhz/272 ). a slight (sub 0.5%) pitch shift will therefore results in the 8khz and 44.1khz audio data and (more importantly) the user must ensure that
wm8734 advanced information w ai rev 2.2 november 2001 28 the data across the digital interface is correctly synchronised at the 8.021khz and 44.117khz rates. the exact sample rates supported for all combinations are defined by the relationships in table 14 below. actual sampling rate target sampling rate bosr=0 ( 250fs) bosr=1 (272fs) khz khz khz 8 8.021 8 12mhz/(250 x 48/8) 12mhz/(272 x 11/2) 32 32 12mhz/(250 x 48/32) not available 44.117 44.1 not available 12mhz/272 48 48 12mhz/250 not available 88.235 88.2 not available 12mhz/136 96 96 12mhz/125 not available table 14 usb mode actual sample rates activating dsp and digital audio interface to prevent any communication problems from arising across the digital audio interface the audio interface is disabled (tristate with weak 100k pulldown). once the audio interface and the sampling control has been programmed it is activated by setting the active bit under software control. register address bit label default description 0001001 active control 0 active 0 activate interface 1 = active 0 = inactive table 15 activating dsp and digital audio interface it is recommended that between changing any content of digital audio interface or sampling control register that the active bit is reset then set. software control interface the software control interface may be operated using either a 3-wire (spi-compatible) or 2-wire mpu interface. selection of interface format is achieved by setting the state of the mode pin. in 3-wire mode, sdin is used for the program data, sclk is used to clock in the program data and csb is used to latch in the program data. in 2-wire mode, sdin is used for serial data and sclk is used for the serial clock. in 2-wire mode, the state of csb pin allows the user to select one of two addresses. unused register bits should always be set to ?0? unless specified otherwise. selection of serial control mode the serial control interface may be selected to operate in either 2 or 3-wire modes. this is achieved by setting the state of the mode pin. mode interface format 0 2 wire 1 3 wire table 16 control interface mode selection
wm8734 advanced information w ai rev 2.2 november 2001 29 3-wire (spi compatible) serial control mode the wm8734 can be controlled using a 3-wire serial interface. sdin is used for the program data, sclk is used to clock in the program data and csb is use to latch in the program data. the 3-wire interface protocol is shown in figure 22. csb sclk sdin b15 b6 b7 b8 b9 b10 b11 b12 b13 b14 b1 b2 b3 b4 b5 b0 figure 22 3-wire serial interface notes: 1. b[15:9] are control address bits 2. b[8:0] are control data bits 2-wire serial control mode the wm8734 supports a 2-wire mpu serial interface. the device operates as a slave device only. the wm8734 has one of two slave addresses that are selected by setting the state of pin 10, (csb). sdin sclk ack r addr ack data b15-8 stop start data b7-0 r/w ack figure 23 2-wire serial interface notes: 1. b[15:9] are control address bits 2. b[8:0] are control data bits csb state (default = low) address 0 0011010 1 0011011 table 17 2-wire mpu interface address selection to control the wm8734 on the 2-wire bus the master control device must initiate a data transfer by establishing a start condition, defined by a high to low transition on sdin while sclk remains high. this indicates that an address and data transfer will follow. all peripherals on the 2-wire bus respond to the start condition and shift in the next eight bits (7-bit address + r/w bit). the transfer is msb first. the 7-bit address consists of a 6-bit base address + a single programmable bit to select one of two available addresses for this device (see table 24). if the correct address is received and the r/w bit is ?0?, indicating a write, then the wm8734 will respond by pulling sdin low on the next clock pulse (ack). the wm8734 is a write only device and will only respond to the r/w bit indicating a write. if the address is not recognised the device will return to the idle condition and wait for a new start condition and valid address. once the wm8734 has acknowledged a correct address, the controller will send eight data bits (bits b[15]-b[8]). wm8734 will then acknowledge the sent data by pulling sdin low for one clock pulse. the controller will then send the remaining eight data bits (bits b[7]-b[0]) and the wm8734 will then acknowledge again by pulling sdin low.
wm8734 advanced information w ai rev 2.2 november 2001 30 a stop condition is defined when there is a low to high transition on sdin while sclk is high. if a start or stop condition is detected out of sequence at any point in the data transfer then the device will jump to the idle condition. after receiving a complete address and data sequence the wm8734 returns to the idle state and waits for another start condition. each write to a register requires the complete sequence of start condition, device address and r/w bit followed by the 16 register address and data bits. note that the 16 bit control word is made up of 7 address bits, b[15:9], and 9 data bits, b[8:0]. these are transmitted as 2 blocks of 8 bits. the first block contains 7 address bits and the data hsb. the second block contains the 8 data lsbs. power down modes the wm8734 contains power conservation modes in which various circuit blo cks may be safely powered down in order to conserve power. this is software programmable as shown in the table below. register address bit label default description 0 lineinpd 1 line input power down 1 = enable power down 0 = disable power down 2 adcpd 1 adc power down 1 = enable power down 0 = disable power down 3 dacpd 1 dac power down 1 = enable power down 0 = disable power down 4 outpd 1 line output power down 1 = enable power down 0 = disable power down 0000110 power down control 7 poweroff 1 power off device 1 = device power off 0 = device power on table 18 power conservation modes software control when writing to the powerdown register bits 1,5 & 6 should be set to ?1?. the power down control can be used to either a) permanently disable functions when not required in certain applications or b) to dynamically power up and down functions depending on the operating mode, e.g.: during playback or record. please follow the special instructions below if dynamic implementations are being used. lineinpd: simultaneously powers down both the line inputs. this can be done dynamically without any audible effects either on the adc or to the line outputs in bypass mode. this is of use when the device enters playback, pause or stop modes or the microphone input has been selected. adcpd: powers down the adc and adc filters. if this is done dynamically then audible pops will result if any signals were present through the adc. to overcome this whenever the adc is to be powered down, either mute the microphone input (mutein) or mutelinein, then change adcpd. this is of use when the device enters playback, pause or stop modes regardless of whether microphone or line inputs are selected. dacpd: powers down the dac and dac digital filters. if this is done dynamically then audible pops will result unless the following guidelines are followed. in order to prevent pops, the dac should first be soft-muted (dacmu), the output should then be de-selected from the line and headphone output (dacsel), then the dac powered down (dacpd). this is of use when the device enters record, pause, stop or bypass modes. the device can be put into a standby mode (standby) by powering down all the audio circuitry under software control as shown in table 18. provision has been made to independently power off these areas according to table 19.
wm8734 advanced information w ai rev 2.2 november 2001 31 power off dacpd adcpd lineinpd outpd description 0 1 1 1 1 standby table 19 standby mode in standby mode the control interface, a small portion of the digital and areas of the analogue circuitry remain active. the active analogue includes the analogue vmid reference so that the analogue line inputs, line outputs and headphone outputs remain biased to vmid. this reduces any audible effects caused by dc glitches when entering or leaving standby mode. the device can be powered off by writing to the poweroff bit of the power down register. in poweroff mode the control interface and a small portion of the digital remain active. the analogue vmid reference is disabled. power off dacpd adcpd lineinpd outpd description 1 x x x x poweroff table 20 poweroff mode
wm8734 advanced information w ai rev 2.2 november 2001 32 register map the complete register map is shown in table 21. the detailed description can be found in the relevant text of the device description. there are 8 registers with 9 bits per register. these can be controlled using either the 2 wire or 3 wire mpu interface. register address bit label default description 4:0 linvol[4:0] 10111 ( 0db ) left channel line input volume control 11111 = +12db . . 1.5db steps down to 00000 = -34.5db 7 linmute 1 left channel line input mute to adc 1 = enable mute 0 = disable mute 0000000 left line in 8 lrinboth 0 left to right channel line input volume and mute data load control 1 = enable simultaneous load of linvol[4:0] and linmute to rinvol[4:0] and rinmute 0 = disable simultaneous load 4:0 rinvol[4:0] 10111 ( 0db ) right channel line input volume control 11111 = +12db . .1.5db steps down to 00000 = -34.5db 7 rinmute 1 right channel line input mute to adc 1 = enable mute 0 = disable mute 0000001 right line in 8 rlinboth 0 right to left channel line input volume and mute data load control 1 = enable simultaneous load of rinvol[4:0] and rinmute to linvol[4:0] and linmute 0 = disable simultaneous load 0000100 analogue audio path control 4 dacsel 0 dac select 1 =select dac 0 = don?t select dac 0 adchpd 0 adc high pass filter enable 1 = enable high pass filter 0 = disable high pass filter 2:1 deemp[1:0] 00 de-emphasis control 11 = 48khz 10 = 44.1khz 01 = 32khz 00 = disable 3 dacmu 1 dac soft mute control 1 = enable soft mute 0 = disable soft mute 0000101 digital audio path control 4 hpor 0 store dc offset when high pass filter disabled 1 = store offset 0 = clear offset
wm8734 advanced information w ai rev 2.2 november 2001 33 register address bit label default description 0 lineinpd 1 line input power down 1 = enable power down 0 = disable power down 2 adcpd 1 adc power down 1 = enable power down 0 = disable power down 3 dacpd 1 dac power down 1 = enable power down 0 = disable power down 4 outpd 1 line output power down 1 = enable power down 0 = disable power down 0000110 power down control 7 poweroff 1 poweroff mode 1 = enable poweroff 0 = disable poweroff 1:0 format[1:0] 10 audio data format select 11 = dsp mode, frame sync + 2 data packed words 10 = i 2 s format, msb-first left-1 justified 01 = msb-first, left justified 00 = msb-first, right justified 3:2 iwl[1:0] 10 input audio data bit length select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits 4 lrp 0 daclrc phase control (in left, right or i 2 s modes) 1 = right channel dac data when daclrc high 0 = right channel dac data when daclrc low (opposite phasing in i 2 s mode) or dsp mode a/b select (in dsp mode only) 1 = msb is available on 2nd bclk rising edge after adclrc/daclrc rising edge 0 = msb is available on 1st bclk rising edge after adclrc/daclrc rising edge 5 lrswap 0 dac left right clock swap 1 = right channel dac data left 0 = right channel dac data right 6 ms 0 master slave mode control 1 = enable master mode 0 = enable slave mode 0000111 digital audio interface format 7 bclkinv 0 bit clock invert 1 = invert bclk 0 = don?t invert bclk
wm8734 advanced information w ai rev 2.2 november 2001 34 register address bit label default description 0 usb/ normal 0 mode select 1 = usb mode (250/272fs) 0 = normal mode (256/384fs) 1 bosr 0 base over-sampling rate 0 = 256fs 1 = 384fs 5:2 sr[3:0] 0000 adc and dac sample rate control 0001000 sampling control 6 clkidiv2 0 core clock divider select 1 = core clock is mclk divided by 2 0 = core clock is mclk 0001001 active control 0 active 0 activate interface 1 = active 0 = inactive table 21 register map description note: unused register bits should be set to ?0? except when writing to register 0000110, when bits 1,5 and 6 should be set to ?1?. digital filter characteristics the adc and dac employ different digital filters. there are 4 types of digital filter, called type 0, 1, 2 and 3. the performance of types 0 and 1 is listed in the table below, the responses of all filters is shown in the proceeding pages. parameter test conditions min typ max unit adc filter type 0 (usb mode, 250fs operation) +/- 0.05db 0 0.416fs passband -6db 0.5fs passband ripple +/- 0.05 db stopband 0.584fs stopband attenuation f > 0.584fs -60 db adc filter type 1 (usb mode, 272fs or normal mode operation) +/- 0.05db 0 0.4535fs passband -6db 0.5fs passband ripple +/- 0.05 db stopband 0.5465fs stopband attenuation f > 0.5465fs -60 db high pass filter corner frequency -3db -0.5db -0.1db 3.7 10.4 21.6 hz dac filter type 0 (usb mode, 250fs operation) +/- 0.03db 0 0.416fs passband -6db 0.5fs passband ripple +/-0.03 db stopband 0.584fs stopband attenuation f > 0.584fs -50 db dac filter type 1 (usb mode, 272fs or normal mode operation) +/- 0.03db 0 0.4535fs passband -6db 0.5fs passband ripple +/- 0.03 db stopband 0.5465fs stopband attenuation f > 0.5465fs -50 db table 22 digital filter characteristics
wm8734 advanced information w ai rev 2.2 november 2001 35 terminology 1. stop band attenuation (db) - the degree to which the frequency spectrum is attenuated (outside audio band) 2. pass-band ripple ? any variation of the frequency response in the pass-band region dac filter responses -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 24 dac digital filter frequency response ?type 1 figure 25 dac digital filter ripple ?type 1 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 response (db) frequency (fs) figure 26 dac digital filter frequency response ?type 2 figure 27 dac digital filter ripple ?type 2 adc filter responses -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs)
wm8734 advanced information w ai rev 2.2 november 2001 36 figure 28 adc digital filter frequency response ?type 1 figure 29 adc digital filter ripple ?type 1 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 response (db) frequency (fs) figure 30 adc digital filter frequency response ?type 2 figure 31 adc digital filter ripple ?type 2 adc high pass filter the wm8734 has a selectable digital high pass filter to remove dc offsets. the filter response is characterised by the following polynomial. digital de-emphasis characteristics -10 -8 -6 -4 -2 0 0 2000 4000 6000 8000 10000 12000 14000 16000 response (db) frequency (fs) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 2000 4000 6000 8000 10000 12000 14000 16000 response (db) frequency (fs) figure 32 de-emphasis frequency response (32khz) figure 33 de-emphasis error (32khz) -10 -8 -6 -4 -2 0 0 5000 10000 15000 20000 response (db) frequency (fs) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 5000 10000 15000 20000 response (db) frequency (fs) h(z) = 1 ? z -1 1 ? 0.9995 z -1
wm8734 advanced information w ai rev 2.2 november 2001 37 figure 34 de-emphasis frequency response (44.1khz) figure 35 de-emphasis error (44.1khz) -10 -8 -6 -4 -2 0 0 5000 10000 15000 20000 response (db) frequency (fs) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 5000 10000 15000 20000 response (db) frequency (fs) figure 36 de-emphasis frequency response (48khz) figure 37 de-emphasis error (48khz)
wm8734 advanced information w ai rev 2.2 november 2001 38 recommended external components wm8734 codec vmid avdd agnd 10 11 3.3v 0.4 f 0.1 f 10 f + 12 rlinein 5k ? 5k ? 47pf + 470nf 13 llinein 5k ? 5k ? 47pf + 470nf 14 dbvdd dcvdd 3.3v dgnd 3.3v + + 2 1 20 3-wire or 2-wire mpu interface 3-wire interface 2-wire interface sdin 17 csb 16 sclk 18 mode 15 10 f0.1 f 10k ? 3.3v mclk 19 + 10 f daclrc dacdat adclrc adcdat bclk 3 audio serial data i/f 5 4 7 6 lout + 470nf 47k ? 100 ? 8 rout + 470nf 47k ? 100 ? 9 figure 38 external components diagram
wm8734 advanced information w ai rev 2.2 november 2001 39 package dimensions (ssop) notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.20mm. d. meets jedec.95 mo-150, variation = ae. refer to this specification for further details. dm0015.a ds: 20 pin ssop (7.2 x 5.3 x 1.75 mm) symbols dimensions (mm) min nom max a ----- ----- 2.0 a 1 0.05 ----- ----- a 2 1.65 1.75 1.85 b 0.22 ----- 0.38 c 0.09 ----- 0.25 d 6.90 7.20 7.50 e 0.65 bsc e 7.40 7.80 8.20 e 1 5.00 5.30 5.60 l 0.55 0.75 0.95 0 o 4 o 8 o ref: jedec.95, mo-150 c l gauge plane 0.25 a a2 a1 seating plane -c- 0.10 c 10 1 d 11 20 e b e1 e
wm8734 advanced information w ai rev 2.2 november 2001 40 package dimensions (qfn) dm023.c fl: 28 pin qfn plastic package 5 x 5 x 0.9 mm body, 0.50 mm lead pitch 14 13 b 15 c aaa l d2/2 d2 e2 e2/2 see detail b index area (d/2 x e/2) c aaa 2 x 2 x c c 0.08 c ccc a a1 (a3) seating plane b c ccc m a detail b terminal tip r 1 notes: 1. dimension b applied to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 2. falls within jedec.95, mo-220 with the exception of d2, e2, a3: d2,e2: larger pad size chosen which is just outside jedec specification a3: nominal value less than jedec 3. all dimensions are in millimetres 4. this drawing is subject to change without notice. symbols dimensions (mm) min nom max note a 0.80 0.90 1.00 b 0.18 0.23 0.30 1 d 5.00 bsc d2 3.2 3.3 3.4 e 5.00 bsc e2 3.2 3.3 3.4 e 0.5 bsc l 0.35 0.4 0.45 2 2 a1 0 0.02 0.05 a3 0.2 ref top view b b a a datum e r b(min)/2 aaa 0.15 ccc 0.10 ref: jedec.95, mo-220, variation vhhd-1 tolerances of form and position 2 27 28 1 2 7 8 21 22 e d e
wm8734 advanced information w ai rev 2.2 november 2001 41 revision history revision originator change date history 2.2 ev 19/11/2001 front page: added mention of qfn package; changed sclk to input only in block diagram (was previously drawn as i/o) page 3: added qfn pinout diagram, pin description, and order info pages 2/3, pin descriptions: sdin changed to i/o (was input only) page 41: added qfn package diagram page 42: added revision history
wm8734 advanced information w ai rev 2.2 november 2001 42 important notice wolfson microelectronics ltd (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. all products are sold subject to the wm terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wm warrants performance of its products to the specifications applicable at the time of sale in accordance with wm?s standard warranty. testing and other quality control techniques are utilised to the extent wm deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wm assumes no liability for applications assistance or customer product design. wm does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of wm covering or relating to any combination, machine, or process in which such products or services might be or are used. wm?s publication of information regarding any third party?s products or services does not constitute wm?s approval, license, warranty or endorsement thereof. reproduction of information from the wm web site or datasheets is permissable only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information with alteration voids all warranties provided for an associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. resale of wm?s products or services with statements different from or beyond the parameters stated by wm for that product or service voids all express and any implied warranties for the associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. address: wolfson microelectronics ltd 20 bernard terrace edinburgh eh8 9nx united kingdom tel :: +44 (0)131 667 9386 fax :: +44 (0)131 667 5176 email :: sales@wolfsonmicro.com

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